1. Field of the Invention
The present invention relates to a technique for estimating a PLL jitter amount on the basis of a simultaneously operating signal noise caused by the simultaneous operations of input/output signals of a plurality of pins in a semiconductor device.
2. Description of the Related Art
Conventionally, a power supply oscillation that occurs between a ground or a power supply pin of a device package and a ground or a power supply reference level of a die within a device is called a ground bounce or a power supply sag, and is one of main causes of erroneous switching in a high-speed device.
Recently, an FPGA (Field Programmable Gate Array) has attracted attention as a semiconductor device for which a user can freely set the arrangement of pins, a circuit configuration, the standard of I/O signals (LVTTL, LVCMOS, HSTL, etc.), an output current value (12 mA, 8 mA, 4 mA, etc.), a through rate control (FAST or SLOW), and the like. Because the number of I/O pins and the speeds of interface signals on the FPGA have been increasing, a lot of output pins simultaneously operate. As a result, the above described ground bounce or power supply sag becomes conspicuous. These phenomena are generally called a simultaneously operating signal noise (SSN (Simultaneous Switching Noise) or an SSO (Simultaneous Switching Output) noise), or a crosstalk noise.
Additionally, on the FPGA, a PLL (Phase Locked Loop) for controlling the stable oscillation of an internal clock is mounted, and a dedicated or shared PLL power supply terminal is provided. The PLL power supply voltage of the die within the device is fluctuated by the crosstalk noise (SSO noise) of I/O signals to/from the PLL power supply terminal and wires within the package, and a PLL jitter amount therefore increases.
The amounts of occurring SSO noise and PLL jitter fluctuate depending on the arrangement of pins on the FPGA. Therefore, the amounts of occurring SSO noise and PLL jitter must be estimated based on the arrangement of pins on the FPGA in a design phase of a PCB (Printed Circuit Board) mounting the FPGA in order to operate an FPGA device at suitable timing.
General-purpose circuit analysis simulator software called SPICE (Simulation Program with Integrated Circuit Emphasis), which was developed by the integrated circuit group of Electronics Research Laboratory and the EECS department of the University of California, Berkeley, is known as the conventional technology for simulating an SSO noise.
Additionally, Japanese Published Unexamined Patent Applications Nos. H10-127089 and 2004-205095 disclose the relevant conventional technology.
However, the simulator such as SPICE, etc. requires an enormous amount of time to simulate an SSO noise although it can simulate the SSO noise with relatively high accuracy.
Conventionally, neither a pin arrangement nor an operating state is definitely laid down as the standard of PLL jitter on an FPGA, and how a PLL jitter amount fluctuates depending on a change in a pin arrangement or an operating state is not stipulated. Accordingly, there is a problem that a PLL and an FPGA device cannot be properly operated in some cases depending on a pin arrangement or an operating state.